(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit system which includes a first power terminal for supplying a source power voltage to an output unit of the system, and a second power terminal for supplying a source power voltage to an internal unit of the system other than the output unit.
(2) Description of the Related Art
Recently, microprocessors having high processing speeds have been developed, and there are demands for semiconductor memories which provide high processing speeds in association with the microprocessors. A synchronous dynamic random access memory (which will be called a synchronous DRAM) which provides a high processing speed is also demanded.
The synchronous DRAMs have a first power terminal for supplying source power to output units, and a second power terminal for supplying source power to internal units other than the output units. The source power is supplied to a group of two or four output units and the internal units independently of each other, and the charging and discharging of a great capacitance in some tens of picofarads (pF) is performed at high speeds. This structure of the synchronous DRAMs ensures stable operations of the output units requiring a large current consumption.
Typically, in the synchronous DRAMs, a source power voltage VDDQ supplied to the output units and a source power voltage VDD supplied to the internal units are the same. For example, both the source power voltages VDDQ and VDD are equal to 3.3 volts. However, the source power voltages VDDQ and VDD in some type of the synchronous DRAMs may be different from each other.
A system which utilizes a plurality of the synchronous DRAMs provided therein is known. Data terminals of the synchronous DRAMs are connected in common to an external data bus.
When read-data signals are input to some of the synchronous DRAMs during operation of the above-mentioned system, the data terminals of these synchronous DRAMs drive the external data bus at one of two different voltage levels, and the data terminals of the other synchronous DRAMs are set in a high-impedance state (or the opened condition). This prevents the driving of the external data bus at one of the two voltage levels by the other synchronous DRAMs. Therefore, it is possible to prevent the flow of a large amount of short-circuit current between the synchronous DRAMs through the sharing external data bus.
FIG. 1 shows main elements of a conventional synchronous DRAM. In FIG. 1, reference numeral 1 indicates a data terminal, reference numeral 2 indicates an output unit, and reference numeral 3 indicates a VDDQ power line. The output unit 2 outputs data (DQ) to the data terminal 1. A source power voltage VDDQ (VDDQ=3.3 volts) from the VDDQ power line 3 is supplied to the output unit 2.
In the conventional synchronous DRAM of FIG. 1, an output control unit 4 controls the output unit 2 in accordance with a read-data signal (RD) from a memory core (not shown) of the synchronous DRAM. A source power voltage VDD (VDD=3.3 volts) from a VDD power line 5 is supplied to the output control unit 4.
The source power voltage VDDQ is supplied to the output unit 2. The source power voltage VDD is supplied to the internal units of the conventional synchronous DRAM other than the output unit 2. In the conventional integrated circuit system of FIG. 1, the internal units include the output control unit 4 and a VDD rising edge detecting unit 6.
The source power voltage VDD from the VDD power line 5 is supplied also to the VDD rising edge detecting unit 6. When power is turned on, the VDD rising edge detecting unit 6 detects whether the source power voltage VDD supplied to the internal units other than the output unit 2 is at its rising edge. When the rising edge of the source power voltage VDD is detected, the VDD rising edge detecting unit 6 outputs a detection signal STT (which is set at the high level) to the output control unit 4. In response to this detection signal STT from the VDD rising edge detecting unit 6, the output control unit 4 sets the data terminal 1 of the output unit 2 in the high-impedance state.
In the conventional synchronous DRAM, if the source power voltage VDD supplied to the internal units other than the output unit 2 is detected as being at the rising edge, the data terminal 1 is set in the high-impedance state. This prevents the external data bus from being driven at one of the two voltage levels by the synchronous DRAMs sharing the external data bus. Therefore, it is possible to prevent the flow of a large amount of short-circuit current between the synchronous DRAMs through the sharing external data bus.
However, generally, a rising edge of the source power voltage VDDQ supplied to the output unit 2 and a rising edge of the source power voltage VDD supplied to the internal units other than the output unit 2 does not always occur at the same time. Therefore, there is a situation in which the rising edge of the source power voltage VDDQ occurs prior to the occurrence of the rising edge of the source power voltage VDD.
FIG. 2 shows a problem of the conventional synchronous DRAM of FIG. 1 when the rising edge of the source power voltage VDDQ occurs prior to the occurrence of the rising edge of the source power voltage VDD. As shown in FIG. 2, in the conventional synchronous DRAM, a change in the source power voltage VDDQ is indicated by a solid line in FIG. 2, and a change in the source power voltage VDD is indicated by a dotted line in FIG. 2.
In the conventional synchronous DRAM of FIG. 2, if the rising edge of the source power voltage VDD occurs prior to the occurrence of the rising edge of the source power voltage VDDQ, the data terminal 1 is set in the high-impedance state, and it is possible that the flow of a large amount of short-circuit current between the synchronous DRAMs through the sharing external data bus is prevented.
However, as shown in FIG. 2, if the rising edge of the source power voltage VDDQ occurs prior to the occurrence of the rising edge of the source power voltage VDD, the source power voltage VDDQ from the VDDQ power line 3 is supplied to the output unit 2 before the data terminal 1 is set in the high-impedance state. At this time, the conventional synchronous DRAM has a problem in that the flow of a large amount of short-circuit current between the synchronous DRAMs through the external data bus may occur.